1. Field of the Invention
The present invention relates to a semiconductor integrated circuit configured to be capable of autonomously adjusting output impedance.
2. Description of Related Art
When a semiconductor integrated circuit transfers data to the outside, if there exists a mismatch between the output impedance of the output driver of the semiconductor integrated circuit and the impedance of a transmission line connected to the output driver, there occurs reflection of a data signal outputted from the output driver. Generally, impedance of a transmission line has a tendency to hardly vary, but output impedance of a semiconductor integrated circuit has a tendency to easily vary according to a fluctuation of the operating voltage or temperature in the circuit. For this reason, there has been contrived an impedance adjustment circuit that can detect a fluctuation of the impedance and autonomously correct it.
The impedance adjustment circuit capable of autonomously adjusting the impedance is often used in semiconductor integrated circuits operating at a high speed, such as a SRAM (Static Random Access Memory). On the other hand, the impedance adjustment circuit is not so used in semiconductor integrated circuits in which a low power consumption operation is required, such as a DRAM (Dynamic Random Access Memory) and a pseudo-SRAM. For this reason, lowering the power consumption of the impedance adjustment circuit itself has seldom been requested. However, with the increased speed of data transmission of recent years, it becomes indispensable to perform impedance matching even in the DRAM or pseudo-SRAM in order to prevent an incorrect transmission caused by reflection of the output data signal.
The Japanese Unexamined Patent Publication No. 2003-198357 (referred to as “Patent Document 1” hereinafter) discloses a DRAM chip configured to be capable of autonomously adjusting output impedance. The memory chip disclosed in this Patent Document 1 includes an external terminal to be connected to a replica resistor for impedance matching. The memory chip disclosed in this Patent Document 1 constantly compares the impedance of the output driver with the impedance of the replica resistor connected to the external terminal, and changes the size of the output driver according to the comparing result. By this procedure, the memory chip disclosed in the Patent Document 1 adjusts the output impedance of the output driver to be matched with the impedance of the replica resistor connected to the outside of the chip. The output driver used herein is a driver provided for outputting data read from a memory cell to the outside through an I/O terminal. Moreover, in order to control the sequence of the impedance matching operations stated above, there is used an external clock inputted from the outside of the semiconductor integrated circuit.
FIG. 6 shows the main part of a DRAM chip configured to be capable of autonomously adjusting output impedance. Note that FIG. 6 is drafted by the present inventor for describing a problem which the present inventor has found. As shown in FIG. 6, a DRAM chip 7 is connected to a processor 6 through an address bus 61 and a data bus 62. In the configuration components included in the DRAM chip 7, only components related to read access processing performed by the processor 6 and components related to impedance adjustment performed with respect to the data bus 62 are shown in FIG. 6.
An address decoder 12 included in the DRAM chip 7 decodes an input address which is supplied from the address bus 61 to an address input terminal 11, and selects a word line (not shown) and a bit line (not shown) of a memory cell array 13 which are corresponding to the memory cell specified by the input address.
A sense amplifier 14, which is connected to the bit line of the memory cell array 13, amplifies data read from the memory cell array 13 and outputs the amplified data to an output driver 15.
The output driver 15, which is connected to a data output terminal 16, outputs the data read from the memory cell array 13 to the data bus 62.
The output driver 15 is configured to be capable of changing the current driving capability so that the output impedance of the output driver 15 may match with the impedance of the data bus 62 being a transmission line. As a controlling mechanism of the current driving capability of the output driver 15, the DRAM chip 7 includes replica drivers 17P and 17N, comparators 18P and 18N, U/D counters 19P and 19N, and I/O terminals 71P and 71N. These configuration components constitute the impedance adjustment circuit included in the DRAM chip 7.
The replica driver 17P is a driver circuit that is configured similarly to the pull-up side circuit of the output driver 15 including pull-up side transistors and has the same output impedance as that of the pull-up side circuit. The output of the replica driver 17P is connected to the external terminal 71P to which a replica resistor R71 is connected. The replica resistor R71 has the same impedance as the characteristic impedance of the data bus 62. The comparator 18P compares the output voltage level of the replica driver 17P with the voltage level (VDDQ/2 in FIG. 6) which has been set in advance. The U/D counter 19P is counted up or counted down according to the comparing result by the comparator 18P. Furthermore, the DRAM chip 7 is configured to change the current driving capability of the replica driver 17P and the pull-up side circuit of the output driver 15 according to a value of the U/D counter 19P. The configuration described above enables the DRAM chip 7 to achieve matching between the output impedance of the replica driver 17P and the impedance of the replica resistor R71 by converging the retained value of the U/D counter 19P.
Meanwhile, in order to adjust the output impedance of the pull-down side circuit of the output driver 15, the pull-down side of the DRAM chip 7 has configuration components symmetrical to those of the pull-up side described above.
However, the present inventor has recognized that the semiconductor integrated circuit configured to be capable of autonomously adjusting output impedance, such as the DRAM chip disclosed in the Patent Document 1 and the DRAM chip 7 shown in FIG. 6, needs to be provided with an external terminal for exclusive use to be connected to the replica resistor. Accordingly, there is a problem in that the number of terminals that should be provided in the integrated circuit package increases.